Tuo Li

Tuo Li

Associate Professor
Institute of Computing Technology, Chinese Academy of Sciences
Beijing, China

RISC-V Computer Architecture Security Fault Tolerance Trusted Computing
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About

I am an Associate Professor in the State Key Lab of Processors at the Institute of Computing Technology (ICT), Chinese Academy of Sciences. My current research is centered on trusted computing, with broader interests in RISC-V ISA security extensions, microarchitectural side-channel defenses, and soft-error resilience for safety-critical systems. I received my PhD in Computer Science and Engineering from the University of New South Wales (UNSW) in 2014, supervised by Prof. Sri Parameswaran. Before joining ICT CAS, I was a Research Fellow at UNSW CSE / IFCYBER, where I served as Tech Lead on two trustworthy computer architecture projects funded by DSTG Australia.

Research

Trusted Computing

We are investigating hardware root of trust design targeting next-generation computing across cloud, edge, and endpoint platforms. Our work covers secure boot, attestation, and isolation primitives that establish a verifiable foundation for trusted execution on RISC-V. Work in progress.

RISC-V ISA for Memory Safety

Based on the seminal work of SoftBound and lessons learnt from Intel MPX, we created a RISC-V architectural solution (see DAC2021 and DAC2022) for pointer-based memory safety using disjoint metadata (non-fat-pointer). The ISA extension covers both spatial (out-of-bounds) and temporal (use-after-free) errors with moderate hardware overhead, without the invasive bus changes required by CHERI.

Microarchitectural Timing Channel Mitigation

Meltdown and Spectre-class attacks are among the major computer architecture challenges (see Hennessy and Patterson's Turing Lecture). Our work (see DAC2022 and ArXiv2020) introduces an ISA extension with microarchitectural enhancements on RISC-V rocket chip for strict timing channel isolation between security domains.

Dependable Embedded Processors

Soft errors are transient failures that do not permanently damage hardware but threaten reliability as chip integration density increases. Our goal is efficient architectural solutions for embedded processors (e.g. Leon2/SPARC) to be soft-error-resilient. See IEEE TC 2017 and DATE 2016, in collaboration with CES KIT under DFG Priority Program SPP-1500.

Selected Publications

Tuo Li, Sri Parameswaran
FaSe: Fast Selective Flushing to Mitigate Contention-based Cache Timing Attacks
DAC 2022: 541–546
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Hsu-Kang Dow, Tuo Li, William Miles, Sri Parameswaran
SHORE: Hardware/Software Method for Memory Safety Acceleration on RISC-V
DAC 2021: 289–294
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Tuo Li, Jude Angelo Ambrose, Roshan G. Ragel, Sri Parameswaran
Processor Design for Soft Errors: Challenges and State of the Art
ACM Computing Surveys 49(3): 57:1–57:44 (2016)
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Keywords from publications:

FPGA Memory Safety Genomics Soft-Error Resilience Timing Isolation ORAM Checkpoint Recovery Cache Timing Attacks RISC-V Approximate Computing Side-Channel Security Performance Monitoring Embedded Processors Fault Tolerance Radiation Effects Multicore Systems Hardware Trojan Computer Architecture Microarchitecture ISA Extension Transient Execution Hardware Security Safety-Critical Error Correction Vulnerability TMR Secure Computing Automotive

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