Tuo Li

Associate Professor
Institute of Computing Technology, Chinese Academy of Sciences
Address: 6 Kexueyuan South Road, Haidian District, Beijing, 100190 China
Email: lituo at ict dot ac dot cn

About

I am an Associate Professor in the State Key Laboratory of Processors (previously, Computer Architecture), at the Institute of Computing Technology (ICT), CAS. I received a PhD in Computer Science and Engineering from the University of New South Wales (UNSW) in 2014, under the supervision of Prof. Sri Parameswaran. I am very grateful to have the opportunity to work with CES at KIT led by Prof. Jörg Henkel during my PhD study. Before joining ICT CAS, I was a Research Associate at UNSW, where I worked as the Tech Lead/Architect on two trustworthy computer architecture projects, with DSTG Australia. I review for conferences and journals, such as CCS, DAC, ICCAD, DATE, IEEE TC, IEEE TDSC, IEEE TCAD, IEEE TVLSI, etc. My publication records can be found at DBLP and Google Scholar. My open-source activites (mostly about RISC-V) can be found at GitHub.

We are hiring! We are looking for a junior or early-stage researcher (CHN national) to join our team. If you are interested in processor security research and want to work with us, please contact. We also have internship and exchange positions open for postgraduate students.

Research

My main research areas are computer architecture, computer security, and fault tolerance. I am interested in innovating processor architecture for trustworthy computing. My recent works are regarding security-enhanced RISC-V processor architectures against timing side channels and memory safety vulnerabilities.

Selected Publications

• Tuo Li, Sri Parameswaran: FaSe: Fast Selective Flushing to Mitigate Contention-based Cache Timing Attacks. DAC 2022: 541-546 (2022) pdf bibtex
• Hsu-Kang Dow, Tuo Li, Sri Parameswaran: HWST128: Complete Memory Safety Accelerator on RISC-V with Metadata Compression. DAC 2022: 709-714 (2022) pdf bibtex
• Hsu-Kang Dow, Tuo Li, William Miles, Sri Parameswaran: SHORE: Hardware/Software Method for Memory Safety Acceleration on RISC-V. DAC 2021: 289-294 (2021) pdf bibtex
• Tuo Li, Bradley Hopkins, Sri Parameswaran: SIMF: Single-Instruction Multiple-Flush Mechanism for Processor Temporal Isolation. ArXiv Preprint. (2020) pdf bibtex
• Tuo Li, Muhammad Shafique, Jude Angelo Ambrose, Jörg Henkel, Sri Parameswaran: Fine-Grained Checkpoint Recovery for Application-Specific Instruction-Set Processors. IEEE Trans. Computers 66(4): 647-660 (2017) pdf bibtex
• Tuo Li, Jude Angelo Ambrose, Roshan G. Ragel, Sri Parameswaran: Processor Design for Soft Errors: Challenges and State of the Art. ACM Comput. Surv. 49(3): 57:1-57:44 (2016) pdf bibtex

Services

• ASP-DAC 2024 TPC member and session chair

Advised Students

• Daniel Rosengarten, Rollback Features for RISC-V Processor, Undergraduate Thesis, UNSW, 2021
• Wei Leong Soon, Code and Control Integrity for RISC-V Processor, Undergraduate Thesis, UNSW, 2021
• Andrew Ross, Checkpointing on RISC-V Processor, Undergraduate Thesis, UNSW, 2019
• Yikai Wang, Memory Isolation in Multi-Core RISC-V System-on-Chip, Summer Research Project, UNSW, 2018
• Jing Gong, Hardware Memory Address Remapping for RISC-V Processor, Summer Research Project, UNSW, 2018
• William Miles, Architectural Support for Spatial Memory Error Checking in RISC-V Processor, Summer Research Project, UNSW, 2018
• Aaron Lai, A Study of Instruction Set Customization in Different RISC-V Processor Variants and Tools, Taste of Research, UNSW, 2017

Useful Things

• Tips and Guidance for Students Writing Papers and Reports (Courtesy: Prof. Gernot Heiser)
• Learn to speak vim -- verbs, nouns, and modifiers!